Foundation of rf CMOS and SiGe BiCMOS technologies

IBM Journal of Research and Development, Mar/May 2003 by Dunn, James S, Ahlgren, David C, Coolbaugh, Douglas D, Feilchenfeld, Natalie B, Et al

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

1. Introduction

Silicon-germanium (SiGe) BiCMOS technology, which achieved its first manufacturing qualification in 1996, is now in its fourth lithographic generation of development. This class of technology integrates high-performance heterojunction bipolar transistors (HBTs) with state-of-the-art CMOS technology. Key technology characteristics for the four generations have been reported by IBM [1-4]. All generations of BiCMOS technology are compatible with an associated IBM CMOS technology in devices, metallization (interconnects), and ASIC design system. Figure 1 is a SiGe BiCMOS chart showing the evolution of performance and minimum lithographic feature size together with some derivative technologies. As shown in Figure 2, the HBT cutoff frequency [function of]^sub T^ has improved from 47 GHz in the 0.5-[mu]m generation to 210 GHz in the 0.13-[mu]m generation. The pace of development continues unabated, and there are no apparent barriers to scaling the SiGe HBTs beyond 210 GHz.

The SiGe HBT performance has been significantly improved by a combination of vertical and lateral scaling. Structural improvements included shrinking the emitter width and reducing layer thicknesses for the first three generations and migrating to a new raised extrinsic base (RXB) structure for the 0.13-[mu]m generation. Vertical profile scaling included increasing the drift field by increasing the Ge concentration and reducing the graded base width, adding carbon (C) to decrease diffusion, reducing the thickness of the collector epitaxial layer, and minimizing the emitter thermal cycle. In the 0.13-[mu]m generation, vertical and lateral profile scaling has led to a reduction in the parasitics of the HBT, especially in the base, collector, and emitter resistances (R^sub B^, R^sub C^, R^sub E^) and total collector-base capacitance (C^sub CB^). Coupled with the increased [function of]^sub T^, this reduction in parasitics is expected to lead to an increased [function of]^sub max^ (the maximum frequency of oscillation of a device, often referred to as U, for unilateral matched power gain, or MAG, for maximum available gain) in the devices. All devices in the production technologies must pass stringent quality and reliability tests [5]. Both the 120-GHz and 210-GHz technologies exhibit collector-emitter breakdown voltage with base open circuit (BV^sub CEO^) values around 2 V, but this is not a serious concern, because in typical circuits the base is biased through a finite resistance and the true HBT breakdown voltage is between BV^sub CER^ and BV^sub CES^ (typically between 3.5 V and 6.5 V. It is more important to know the safe operation area and how large signal parameters vary as a function of use condition [6, 7].

In contrast to the trickle of early circuits [8], there is now a flood of new SiGe products in almost every wired and wireless application area. A sample of the wide variety of SiGe BiCMOS circuits illustrates the wide-ranging applicability of these technologies (Table 1).

An important aspect of any SiGe BiCMOS technology is the yieldable HBT device count. There are now products with HBT device counts greater than 100 000. A good example is a 68 x 69-cross-point switch1 which contains more than 100 000 SiGe HBTs. The largest chip to date is a 10.8 x 10.8-mm OC-48c SONET/SDH mapper with integrated serializer/deserializer integrated clock recovery (CDR) and clock synthesis (CSU).2 This highly integrated mixed-signal circuit includes 6000 HBTs and 1.2 million CMOS transistors.

The 0.5-[mu]m and 0.25-[mu]m SiGe BiCMOS technologies are ideal for many wireless applications. Areas of analog sections do not scale with decreasing lithography, which reduces the incentive to migrate toward more advanced lithography ground rules [3]. Consequently, a full suite of passive devices is required for any highly integrated mixed-signal chip. The focus in resistors is to achieve good tolerance [10% on polysilicon (poly) and single-crystal silicon] and reduced parasitic capacitance. For the most stringent requirements, back-end-of-line (BEOL3) thin-film resistors are being added [3]. The thrust for varactors is improved tunability, while maintaining linearity, and high Q (quality factor) values. Capacitors, both front-end-of-line (FEOL) MOS and metallization-based MIM, require higher capacitance per unit area to provide analog area scaling. The performance of spiral inductors continues to be improved by thick metals in spite of skin-effect concerns. Further enhancements include multiple layers of thick metal, deep-trench mazes under the inductor, and polysilicon ground shields.4 These features, which are discussed in detail in the section devoted to passive elements, result in passives that are much better than those in conventional silicon CMOS and similar to passives in GaAs ICs.