Low-power circuits and technology for wireless digital systems

IBM Journal of Research and Development, Mar/May 2003 by Kosonocky, Stephen V, Bhavnagarwala, Azeez J, Chin, Kenneth, Gristede, George D, Et al

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.

Introduction

As CMOS technology scales to deep-submicron dimensions, highly integrated system-on-a-chip (SoC) circuits can transform computing performance levels previously seen only on desktop computers to performance levels on small, handheld wireless devices. The capability for highspeed, low-power wireless computation opens up exciting new possibilities and applications. Wristwatch computers, such as the IBM WatchPad* or WorkPad*, or a cellular telephone with video streaming connected to a server through wireless LANs, are just a few examples. Simple scaling of conventional static CMOS circuits by technology alone will not produce the optimal low-power design. As we approach the limits of CMOS technology scaling, harnessing the computing performance made possible by these advanced silicon transistors in battery-operated devices becomes very challenging. For these, power becomes a main focus, and new circuit techniques and design methodologies arc necessary to maximize the use of deep-submicron technology while maintaining an acceptable power consumption level. This paper begins by describing deep-submicron CMOS technology limitations, followed by low-power circuit techniques and multi-threshold design methodologies. Active well bias and power gating techniques are then described, followed by an in-depth study of latches and data retention, since this is often a critical portion of overall power consumption. The final sections address architectural considerations, such as the use of parallelism, and power analysis of a third-generation (3G) mobile phone system.

Technology

CMOS technology continues to scale into deep-submicron levels, driven predominantly by performance requirements for desktop workstations and data servers. As MOS transistor channel lengths scale below 100 nanometers and device gate-oxide isolation scales below two nanometers, power consumption due to component leakage begins to surpass dynamic power. These parasitic leakage components are scaling faster than the dynamic switching power components [1, 2]. Technology scaling forces a lower bound on device threshold voltage due to increased subthreshold leakage. This lower bound causes traditional low-power techniques such as power-supply scaling to become less effective. Figure 1 shows an inverter delay with a fan-out of 4 (FO4) for a bulk 0.13-[mu]m CMOS technology as a function of the ratio of supply voltage (V^sub dd^) and threshold voltage (V^sub t^). As can be seen in the figure, voltage scaling can be used efficiently to trade off power for performance for V^sub dd^/V^sub t^ ratios above 3, after which further voltage scaling becomes less efficient.

Low-power circuit styles

One approach to circumvent the technology limitations imposed on the circuit is optimizing the circuit style. Static CMOS is one of the most popular circuit styles for VLSI digital systems. This is due primarily to the robust design nature of this style, which can implement reliable circuits with the lowest sensitivity to process variations. Each digital system requires different power-delay and area tradeoffs. To meet these requirements, a number of different logic circuit families have been proposed [4, 5].

The power dissipation in CMOS circuits consists of several main components, as shown in Equation (1):

The dynamic switching power, P^sub sw^, is the dominant active power dissipation component in CMOS circuits and results from the charging or discharging of the effective capacitive loads. The short-circuit power, P^sub sc^, is due to the existence of a conduction path between power supply and ground during the brief period when a gate switches, and it is usually small compared to P^sub sw^. The static power component, P^sub static^, is not usually a factor in pure CMOS circuit structures, but it is influenced by certain circuit structures such as sense amplifiers. The leakage power component, P^sub leak^, is due to gate-oxide tunneling current, source-to-drain subthreshold conduction, and pn-junction leakage. These leakage components increase, becoming a larger percentage of total power dissipation, as transistor geometries shrink in future technology generations. The first two components of power dissipation, P^sub sw^ and P^sub sc^, result from the actively changing states of the circuit. The last two components of power dissipation, P^sub static^ and P^sub leak^, are always present and do not depend on the state changes of the circuit. The dynamic switching power, P^sub sw^, is defined as