Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies

IBM Journal of Research and Development, Mar/May 2003 by Harame, David L, Newton, Kim M, Singh, Raminderpal, Sweeney, Susan L, Et al

The rapidly expanding telecommunications market has led to a need for advanced rf integrated circuits. Complex rf- and mixed-signal system-on-chip designs require accurate prediction early in the design schedule, and time-to-market pressures dictate that design iterations be kept to a minimum. Signal integrity is seen as a key issue in typical applications, requiring very accurate interconnect transmission-line modeling and RLC extraction of parasitic effects. To enable this, IBM has in place a mature project infrastructure consisting of predictive device models, complete rf characterization, statistical and scalable compact models that are hardware-verified, and a robust design automation environment. Finally, the unit and integration testing of all of these components is performed thoroughly. This paper describes each of these aspects and provides an overview of associated development work.

1. introduction

The rf CMOS and SiGe BiCMOS process technologies are at the leading edge of today's rapidly expanding telecommunications marketplace. Two key application areas in telecommunications are the wireless and wired areas. Examples in the wireless area include cellular telephone radios with protocols such as GSM (Global System for Mobile Communications [1]) and WCDMA (Wideband-Code Division Multiple Access [2]), location systems such as GPS (Global Positioning Satellite System), and wireless connectivity applications such as Bluetooth (2.4-GHz low power connectivity standard [3]) and 802.11x (IEEE wireless LAN standards [4]). Examples of the wired area are synchronous data transmission over optical networks using various protocols such as SONET (synchronous optical network transmission standard [5]) and SDH (synchronous digital hierarchy [6]). Both of these areas require the use of state-of-the-art rf/mixed-signal process technologies and design automation environments.

There is some differentiation between the wired and wireless requirements. The requirements for monolithic wireless chips emphasize technology with superior high-Q passives (inductors, varactors, and capacitors) in addition to the active devices, compact models with accurate noise-figure and distortion analyses, signal integrity analysis, and RLC parasitic extraction. The requirements for monolithic wired chips emphasize process technologies with very-high-speed active devices, rf/analog models of all devices-particularly FET devices, and distributed interconnect models including transmission-line models and field-solver solutions.

As integrated circuit (IC) design becomes more complex and application frequencies continue to rise, the different points in the supply chain must be highly integrated for final product success. The components necessary to successfully enable a silicon chip design are illustrated in Figure 1. There has to be a silicon technology base, a set of vendor CAD tools, and both modeling and design automation activities.

The development of this rf/analog mixed-signal methodology at IBM dates back to the support for the early bipolar technology used in bipolar-based mainframes and, more recently, as an outgrowth of the analog BiCMOS processes initially developed for magnetoresistive (MR) preamplifier applications in the early 1990s. For bipolar mainframes, IBM developed internal modeling and circuit simulation tools1 [7] with an efficient Monte Carlo statistical simulation package. Today, high-performance analog applications utilize the entire BiCMOS device menu and require accurate analog models for all devices. Digital models used to support the standard digital CMOS technologies do not provide sufficient accuracy in predicting the device characteristics in these regimes. In addition, analog circuit designers requested scalable bipolar junction transistor (BJT) models to remove the limitations imposed by an npn device library. These product design requirements defined the direction for the development of more advanced analog models.

In 1990, IBM began using workstation-based OEM design automation tools. In 1992, IBM released the first BiCMOS Cadence**-based2 design kits (starting with the design kit for CBiCMOS3), which included model libraries, symbol libraries, model/layout call-back routines, SKILL** routines (SKILL is the Cadence application extension language), parameterized cells for layout, layout versus schematic checking, design-rule checking, parasitic extraction, and custom graphical user interface tools. This early kit contained all of the basic elements found in today's design kits. In 1994, work began on the development of complex partial response maximum likelihood (PRML) read channel chips, which have a large digital as well as analog content. This required the development of new methodologies to handle analog mixed-signal designs. Work has continued on these tools over the past ten years, leading to a very flexible and robust design kit.

This paper describes the device-level rf/analog enablement methodology practiced at IBM. This enablement methodology is roughly divided into three major sections. The first section focuses on the co-development of the technology using a robust methodology that starts with technology concepts and evolves to early compact models (predictive modeling). Building and calibrating this methodology is a complex process, involving much greater effort than the simple use of vendor tools. The second section describes a characterization and modeling methodology that focuses on a strong rf/analog infrastructure with a statistical emphasis in order to fully simulate the product in manufacturing and predict performance yields (characterization and modeling). Finally, the third section discusses a detailed integrated design automation methodology/framework that includes physical design and verification (with inclusion of complete rf requirements), accurate signal integrity analysis, rf and mixed-signal simulation, and final test verification.