Review and future prospects of low-voltage RAM circuits

IBM Journal of Research and Development, Sep-Nov 2003 by Nakagome, Yoshinobu, Horiguchi, Masashi, Kawahara, Takayuki, Itoh, Kiyoo

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V^sub T^, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

1. Introduction

Standalone and embedded random-access memories (RAMs) have evolved rapidly, and their high density, low power, and low cost have contributed to improving the affordability and performance of electronic systems such as computers, communication systems, and consumer products. In research and development, the density of standalone RAMs has reached the 4-Gb level for dynamic RAMs (DRAMs) [1] and 72-Mb for static RAMs (SRAMs) [2, 3], along with a reduced RAM cell area, as shown in Figure 1 [4].

In embedded RAMs (e-RAMs), recent developments have focused on high speed under low voltages, exemplified by the 1.5-V, 300-MHz, 16-Mb DRAM macro [5] and the 1.5-V, 1-GHz, 24-Mb L3-SRAM cache [6]. Device miniaturization and the rapidly growing demand for mobile or power-aware systems have resulted in an urgent need to reduce power-supply voltage (V^sub CC^) (Figure 2). In standalone RAMs, the standard V^sub CC^ has been reduced to as low as 1.8 V. In e-RAMs, the voltage has been lowered even more, because it is based on that of the logic circuits in microprocessing units (MPUs) [7], reaching below 1.5 V. In particular, the need for e-RAMs to have low-voltage and small memory cells will become increasingly greater, because they are expected to occupy more than 90% of the area of systems-on-a-chip (SoCs) [8]. Reducing the supply voltage to the region below 1 V, however, places three stringent constraints on design [4]:

* Maintaining a high signal-to-noise-ratio (S/N) for RAM cells to operate stably.

* Reducing the leakage currents (especially gate-tunnel current and subthreshold current) in MOSFETs, which increases considerably when the gate-oxide thickness (t^sub ox^) and the threshold voltage (V^sub T^) are reduced.

* Suppressing speed variations that become prominent at low voltages as a result of design parameter variations.

Unless these problems are solved, RAMs will never be able to operate reliably. In addition, the low-power advantage of CMOS circuits will be lost, and we can envision a scenario in which even CMOS SoCs would suffer from huge dissipations of dc power caused by subthreshold currents, as was the case in the recent bipolar and BiCMOS large-scale integration (LSI) eras.

In particular, reducing subthreshold current is extremely important in RAM circuit design and in random logic LSIs. To the best of our knowledge, the importance of reducing subthreshold currents in low-voltage high-speed room-temperature operation LSIs only became apparent in 1991 [9] as a result of innovative developments with 1.5-V high-speed DRAMs [10, 11]. In addition to the preceding reduction schemes through dynamic substrate control and power switches [12], other key solutions to reduce subthreshold current were proposed in the early 1990s [13-17], although these were all in the standby mode. A solution to reduce subthreshold current in the active mode was presented as early as 1993 using a hypothetical 16-Gb DRAM [18]. Although numerous attempts have subsequently been made in both RAMs and logic LSLs, the problem of reducing subthreshold current in the high-speed active mode remains unsolved, especially in random logic LSIs.

2. Trends and challenges with low-voltage RAMs

There are three major issues in producing low-voltage RAMs-stable RAM-cell operation, reduced leakage currents, and suppression of speed variations that are prominent at a lower voltage. However, developments toward creating a smaller cell and lower power dissipation with the simplest processes possible must also be viewed as major concerns for RAMs, because the three issues are closely related to the degree of device miniaturization and low-voltage operation. The intention of this section is to clarify the issues common to both DRAM and SRAM technology trends. For this discussion, we have mainly assumed the standalone RAM chip shown in Figure 3. The chip comprises a RAM array, iterative circuit blocks such as decoders and drivers, peripheral logic circuits, I/O circuits, and on-chip voltage generators that bridge the supply-voltage gap between the memory cell array and peripheral circuits.