Ultralow-power SRAM technology

IBM Journal of Research and Development, Sep-Nov 2003 by Mann, Randy W, Abadeer, W W (Bill), Breitwisch, Matthew J, Bula, O, Et al

An ultralow-standby-power technology has been developed in both 0.18-�m and 0.13-�m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 �m^sup 2^ and 2.34 �m^sup 2^, corresponding respectively to the 0.18-�m and 0.13-�m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25�C and is less than 400 fA per cell at 1.5 V, 85�C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

Introduction

Static random-access memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-end workstation and microprocessor applications. The increased demand for lighter portable electronic applications with extended battery life has fueled the need for technologies that provide low standby power [1, 2], In this work, we describe specific components of the learning required to develop an ultralow-standby-power technology that offers more than three orders of magnitude lower standby power than conventional performance-driven technologies. The development effort was based on highperformance logic rather than DRAM technology [3]. As a result, much of the processing remained consistent with or identical to that used for the high-performance logic technology. The ULP technologies are therefore able to share the same shallow-trench isolation (STI), polysilicon gate definition, suicide, and post-device processing with the base high-performance logic technology [4], This approach provides lower process cost, maintains a common tool set, and shares yield learning with the base high-performance logic processes. A low wafer-processing cost was maintained, since special SRAM cell features such as local interconnects (LIs) or self-aligned contacts (SACs) were not required.

Understanding the specific leakage mechanisms that govern the cell and array leakage as a function of temperature and applied voltage is crucial to controlling the SRAM array standby power. For the present discussion, the leakage mechanisms are classified as being cither parametric (intrinsic) or defect-related in nature. The SRAM array parametric standby leakage contributors include well isolation leakage [5], subthreshold device leakage [6], gate-oxide tunneling [7], reverse-bias diffusion leakage [8], and gate-induced drain leakage (GIDL) [9, 10] for both n-FET and p-FET devices. Implant damage [11], STI stress-induced diffusion leakage [12], suicide defects [13], and contact-related defects [14] must be very carefully controlled or eliminated in order to achieve the ULP leakage obtained. In this paper we review each of the parasitic components and their impact on the overall cell and array standby power. We also discuss specific future challenges to achieving ultralow power for nodes less than 0.13 �m.

Technology overview

A brief summary of some of the more critical ULP technology characteristics of the technologies described in this paper for both the 0.18-�m and 0.13-�m lithography nodes is given in Table 1. Although the device widths and critical dimensions (contact size, n to p spacing, etc.) were reduced for the 0.13-�m technology, the device design, the nominal L^sub poly^ dimension,1 and gate-oxide thicknesses remained the same for both technology nodes. The dimensional tolerances were scaled in a manner consistent with the lithography generation. Both 1.5-V and 2.5-V devices are provided along with dual gateoxide thicknesses of 2.9 nm and 5.2 nm, respectively. The devices optimized at 1.5 V exhibit a saturated threshold voltage (V^sub tsat^ of 0.79 V for the n-FET and -0.79 V for the p-FET. This threshold voltage was selected to achieve the target off-current of

The 2.5-V devices had a threshold voltage of 0.67 V for the n-FET and -0.67 V for the p-FET and a corresponding on-current of 498 �A/�m and 210 �m/�m for an L^sub poly^ of 0.23 �m. The off-current was less than 0.1 pA/�m at 25�C for both n-FET and p-FET. The GIDL was 30 fA/�m for the n-FET and 100 fA/�m for the p-FET. The gate oxide was 5.2 nm by extrapolated capacitance and provided an n-FET inversion oxide thickness of 6.2 nm and a p-FET inversion oxide thickness of 6.4 nm. The junction area capacitance was 1.1 fF/�m^sup 2^ for the n-FET and 1.3 fF/�m^sup 2^ for the p-FET. This device provided I/O and peripheral circuit performance for the stand-alone SRAM operation.

The technology offers the low-resistance contacts and interconnects associated with self-aligned CoSi^sub 2^ suicide processing and planar copper metallization back-end-ofline (BEOL) processing. Although blocking of suicide formation in the SRAM cell was evaluated, the array leakage targets were met with fully suicided arrays.