Fine-grain real-time reconfigurable pipelining

IBM Journal of Research and Development, Sep-Nov 2003 by Kim, Suhwan, Ziesler, Conrad H, Papaefthymiou, Marios C

MPEG video standards specify the upper bounds for picture size, frame rate, and bit rate for various combinations of profiles and levels. For the main-profile at main-level (MP@ML) combination of MPEG-2 in the NTSC-compatible mode, for example, picture size, frame rate, and bit rate are 720 � 480 pixels, 30 frames/s, and 15 Mb/s, respectively. Thus, the maximum throughput requirement for an MPEG-2 MP@ML decoder is 15.552 � 10^sup 6^ samples/s [30 frames/s � (720/16 � 480/16) MB/frame � 6 blocks/MB � 64 pixels/block].

In the MPEG video standard, reconstructed images should be sent to display devices on time. This requirement imposes a real-time constraint on the decompression computation. Therefore, each functional block should be designed to meet the maximum throughput dictated by the standard, even though average data rates can be substantially lower than the upper bound specified by the standard. However, blocks are not required to process data as quickly as possible, as long as they process the data within a specified time. Power savings can thus be achieved by spreading the computation across the time allotted, using the minimum level or resources required to meet throughput requirements.

Furthermore, the time scale over which computations can be spread is limited by practical considerations of the data rates and the cost of buffering. Buffering the decompressed output stream could allow the real-time constraint to be averaged over longer time scales. However, since the output bandwidth is high, the overhead in silicon area is high, and the energy of buffering substantial amounts of the output stream becomes prohibitive. Thus, power savings in this case can be achieved only by One-grain approaches such as our pipeline reconfiguration methodology. Other approaches such as dynamic voltage scaling cannot cope with the short time scales over which voltage scaling must occur.

In general, average data rates in video processing arc often significantly lower than the maximum possible rate. Therefore, although the maximum throughput requirement of the IDCT module is determined by the worst-case number of nonzero DCT coefficients per block, the average number of nonzero DCT coefficients per frame is much smaller than the worst-case one.

In a MAC-based IDCT architecture, the number of nonzero DCT coefficients per block equals the number of multiply-and-accumulate operations required to compute the IDCT of the block. A MAC-based IDCT architecture with eight multipliers processes eight samples per eight cycles. For the maximum throughput of 15.552 � 10^sup 6^ samples/s specified in the MPEG-2 MP@ML video standard, the operating frequency should be at least 15.552 MHz. Similarly, a MAC-based IDCT architecture with four multipliers can be derived from a MAC-based IDCT architecture with eight multipliers using a multiplexer to eliminate the second 1D IDCT. To satisfy the maximum throughput requirement, the remaining ID IDCT would have to process samples at twice the input sample rate, that is, 31.104 MHz. A MAC-based IDCT with two multipliers will have to operate at speeds higher than 62.208 MHz. To achieve these required clock rates at the lowest voltage possible, multipliers in the three IDCT structures should be deeply pipelined. Consequently, pipeline registers consume an increasingly larger fraction of the total dissipated energy, even though overall energy consumption may be reduced.