Application of an SOI 0.12-5m CMOS technology to SoCs with low-power and high-frequency circuits

IBM Journal of Research and Development, Sep-Nov 2003 by Plouchart, Jean-Olivier, Zamdmer, Noah, Kim, Jonghae, Sherony, Melanie, Et al

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

1. Introduction

Many of the power-management schemes currently used in integrated circuits involve adding a power-control system to what are essentially standard circuit building blocks. These power-control networks supply power to the blocks that limit throughput at any given moment and remove it from the blocks that are not supplying useful output. Examples of such power-control schemes include clock gating and variable power supplies. However, when an integrated circuit is a true system-on-a-chip (SoC), encompassing not only digital and memory blocks but also high-frequency analog blocks for wired and wireless communication, power savings become more than a question of the computational efficiency of digital logic. In communications circuits, the power budget depends on such elements as noise levels, isolation, transmission efficiency between subcircuits, and the losses in passive components. SoCs allow the reduction of total system power because the performance and communication specifications of a system can be met with subcircuits and transmission networks that are inherently more energy-efficient than discrete units in a package.

Systems are becoming increasingly integrated, and it is becoming obvious that SoCs are indeed feasible. The first example of the combination of analog and digital blocks was the integration of clock generator phase-locked loops (PLLs) with processors and memory. CMOS circuits with even more analog and radio frequency (RF) function are now being introduced. For example, products such as 5-GHz-wireless-LAN, 1.9-GHz-GSM-cellular, and 10-Gb/s-SONET transceivers [1-3] are being fabricated in 0.18-�m and 0.13-�m technologies, though without integration of the baseband digital signal processor or the microprocessor. As shown in Figure 1(a), the receiving end of a wireless transceiver extracts the information encoded in a carrier modulated at high frequency by filtering and down-converting the antenna signal. After low-frequency analog processing, the signal is converted into the digital domain, where digital processing can be done. An output signal is later transmitted by modulating a high-frequency carrier. One of the key challenges in the design of wireless transceivers is the detection of signals of microvolt amplitude in a multi-carrier environment. With the high gain and low input resistance of today's CMOS transistors, low-noise amplifiers that meet the specifications for wireless communication can answer this challenge.

For wired communication, a transceiver is also used to interface the digital and analog worlds, as shown in Figure 1(b). On the receiving end, after amplification of the input signal, a clock signal is extracted from the bitstream of random data. This clock signal determines the time at which data is sampled by the decision circuit. The high-speed datastream is then demultiplexed-divided into several channels of lower bit rates-for digital processing [Figure 1(c)]. On the transmitting end, the data is aggregated by the multiplexer and then amplified before being sent out to the wired medium.

When combined with a microprocessor, a transceiver makes possible the highly connected, highly intelligent world of embedded electronics envisioned by many. In the integration race, the next step might be the integration of these two functions on the same chip (Figure 1). In the future, wireless and wired transceivers will be seen simply as I/O for microprocessors. As integration continues, we can begin to envision a one-chip solution. This will have a profound and beneficial effect on system cost, power, and size. There are, of course, many barriers to the one-chip solution: Sensitive analog circuits can be disturbed by noise-producing digital logic, the conflicting requirements of analog/RF circuits [4] and digital circuits demand the integration of multiple device types, and there will always be competition from systcm-in-a-package solutions.

In this paper we discuss silicon-on-insulator (SOI) technology, the platform of choice to integrate digital and high-speed analog functions owing to the 10�-lower parasitic capacitance to the substrate of active SOI devices and its inherent higher efficiency and isolation when compared with bulk silicon technologies. SOI ultralargescale integration (ULSI) capabilities and the integration of DRAM and SiGe bipolar transistors on SOI have previously been reported [5-7]. Some aspects of low-power digital design on SOI have also been reported [8, 9]. We show here that, as the number of circuit functions supported by a technology increases and as the performance of those elements increases, the opportunity to save power grows. We first discuss how scaled SOI CMOS provides increased performance and reduced active power in the sub-50-nm-channel-length regime. We then present passive devices integrated with standard interconnect and discuss how they support low-voltage, low-power analog blocks. Next, we discuss circuits designed in this technology and present measurements of high-speed analog circuits and digital signal processing (DSP) building blocks that are state of the art in power dissipation and performance and a circuit library that encompasses low-active-power digital and mixed-signal blocks and allows simple bulk-to-SOI migration. This paper presents new and recently published research and development work done across several IBM organizations on SOI SoC.