Design and validation of a performance and power simulator for PowerPC systems

IBM Journal of Research and Development, Sep-Nov 2003 by Shafi, Hazim, Bohrer, Patrick J, Phelan, James, Rusu, Cosmin A, Peterson, James L

This paper describes the design and validation of a performance and power simulator that is part of the Mambo simulation environment for PowerPC� systems. One of the most notable features of the simulator, designated as Tempo, is the incorporation of an event-driven power model. Tempo satisfies an important need for fast and accurate performance and power simulation tools at the system level. The power and performance predictions from the simulated model of a PowerPC 405GP (or simply 405GP) were validated against a 405GP-based evaluation board instrumented for power measurements using 42 application/dataset combinations from the EEMBC benchmark suite. The average performance and energy-prediction errors were 0.6% and -4.1%, respectively. In addition to describing Tempo, we show examples of how well it can predict the runtime power consumption of a 405GP microprocessor during application execution.

1. Introduction

Computer architects and software developers are faced with a dilemma. In addition to performance, which is the primary design goal of high-end microprocessors, systems, and software, power has emerged as a second primary design metric, especially for embedded systems. Unfortunately, there has been a lack of practical simulation and profiling tools for "what-if" power analysis of new and existing architectures. Performance architectural simulators typically include cycle-accurate models of varying complexity for the systems under investigation. If these simulators are to be practical enough to enable the study of complete applications using realistic datasets, simulation speed will be critical (the classic tradeoff of detail vs. speed is often resolved in favor of the latter).

Further, the power simulation tools that exist today range from very detailed and slow transistor-level SPICE-like [1] models, to higher-level Verilog/VHDL circuit-level power simulators such as PowerTheater** [2] and PowerMill** [3], to the even higher levels of abstraction found in tools such as Wattch [4] that can be integrated with architectural simulators. Our goal has been to integrate cycle-accurate performance and power simulation at the minimum possible speed penalty. Our approach differs from that used in Wattch in that we further abstract the details of power simulation, because our target audience is architects and developers of operating systems and applications. The dilemma of the architects/researchers extends to developers of power-aware software on systems. While they arc typically not as concerned about circuit details involved in arriving at power estimates, they want to know where power is dissipated in their applications. Very few tools can provide such feedback.

Event-based energy tracking models have previously been shown to provide good microprocessor power estimates [5]; hardware registers count the number of occurrences of a limited set of events, allowing an estimate of energy usage over time. Unfortunately, such models are not useful for studying new architectures or systems that do not include event-tracking support in hardware. Since many cycle-accurate simulators are event-driven, we sought to investigate the possibility of modeling the power consumption of a microprocessor by associating energy costs with the occurrence of certain architectural events. If successful, this power modeling approach could be performed at almost no additional simulator runtime overhead; since the important architectural events are already modeled for timing estimates, energy estimates could be computed simply by some additional counting. Our methodology should be extendable to future microprocessors by relying on some of the other, more detailed power simulation techniques to generate our event-based power model during early design stages.

To determine the feasibility of our approach, we decided to model an existing microprocessor: the core processor found in the PowerPC* 405GP [6] system-on-a-chip. Since the 405GP is an existing processor, we could validate our simulator against actual hardware. Our colleagues at the IBM Austin Research Laboratory had designed the Pecan board, a 405GP-based system that has provisions for power measurements. Although the 405GP processor does not include hardware performance counters, it is a relatively simple in-order pipelined processor. If we could build a cycle-accurate version of the 405GP, our simulator could be used for the performance/power tuning of applications and operating systems, despite the lack of hardware performance counters. Enabling such evaluation methodology is very desirable for embedded systems such as the 405GP.

Our efforts have resulted in the development of Tempo, an execution and event-driven cycle-accurate simulator that is part of the Mambo PowerPC simulation environment of the IBM Austin Research Laboratory. Our validation results show that the processor core performance predictions of the simulator have an average error of 0.6%, with a standard deviation of 2.5% on 42 Embedded Microprocessor Benchmarking Consortium (EEMBC) [7] benchmarks when compared to the hardware platform being modeled. The average error in energy predictions was -4.1%, with a standard deviation of 5.1%. In addition, we could model the transient power behavior of applications, which is not possible with many energy models. Tempo can bridge this gap because it can compute the power consumption on a per-cycle basis by accumulating event energies on every cycle.