On the performance and use of dense servers

IBM Journal of Research and Development, Sep-Nov 2003 by Felter, Wesley M, Keller, Tom W, Kistler, Michael D, Lefurgy, Charles, Et al

Where do dense servers fit?

Computing services accessible through the Internet are typically organized in a three-tiered structure, as shown in Figure 1. The first tier consists of an interface to the network, including routers, load balancers, firewalls, and Web servers, among others. Servers deployed in this tier are often referred to as the "edge-of-network servers," or simply "edge servers." The second tier consists of application servers that implement a rich user interface, data presentation, and user interactions with the service. Several technologies exist to implement this tier, including the IBM* WebSphere* [9], the Oracle** Application Server [10], and the Microsoft** .NET [11]. The second tier also connects the first and third tier, with the latter implementing a data warehouse using traditional database technology [12]. The typical workload for a first- and second-tier server is highly parallel, consisting of many independent threads of execution. These workloads are well suited to cluster architectures, in which work is transparently distributed to a set of independent machines. This makes dense servers reasonable candidates for deployment in these two tiers, given that they offer a higher density of processing nodes that can exploit this parallelism.

On the other hand, the database workload on the third tier usually requires frequent inter-thread synchronization to ensure data coherence, and traditional symmetric multiprocessor servers arc better suited for these applications than are dense servers [12]. Therefore, we focus on evaluating dense servers using benchmarks that approximate the typical workloads in the first and second tiers of a Web host.

The Super Dense Server

We have developed a research prototype designated as the Super Dense Server (SDS), which consumes a maximum of 13 W during operation. The SDS consists of a custom-designed board, often referred to as a "blade," that plugs into a standard CompactPCI** [13] backplane. The physical and logical design of the SDS blade is shown in Figure 2. The blade contains an Intel** Ultra Low Voltage (ULV) Pentium** III processor,2 which has a 256K L2 cache and uses SpeedStep** technology [14] to adjust its speed from 300 MHz to 500 MHz. It also includes up to 512 MB of double data rate (DDR) 266 synchronous dynamic random access memory (SDRAM), a universal serial bus (USB) port, two 100-Mb/s Ethernet (designated as Enet in Figure 2) connections along with their physical transceivers (designated as Phy in Figure 2), and a highly integrated Silicon Integrated Systems (SIS) 635 chipsct3 that provides the memory controller, bus controllers, and an integrated drive electronics (IDE) disk interface. Since the chipset was originally intended for mobile devices, it provides a variety of power-saving operation modes from low-latency processor sleep modes to full system hibernation. The SDS blade contains a peripheral component interconnect (PCI) bridge allowing it to interact with standard blades across the CompactPCI backplane. It also contains a service processor that can be controlled remotely through an inter-integrated circuit (I2C) bus. The service processor is responsible for blade power-on, power-off, and hot-swap isolation sequences and supports system management functions.