Functional verification of a frequency-programmable switch chip with asynchronous clock sections

IBM Journal of Research and Development, May-Jul 2004 by Hoppe, B, Arthur-Mensah, B, Chencinski, E W, Joseph, S, Et al

An integral part of the IBM eServer(TM) z990 I/O subsystem is the self-timed interface (STI) switch chip. The STI switch is an application-specific integrated circuit (ASIC) designed to provide high I/O connectivity and high bandwidth within the system. The complexity of the functional verification of the STI switch chip is inherent in the implementation of seventeen logical clock domains and the support of six different STI interfaces with programmable frequencies. The logic within these clock domains is connected via asynchronous interfaces. This paper describes the methodology to verify the functionality of the switch chip with various STIs by introducing a combination of verification techniques. This involves random biased stimulus generation, automated result prediction checking, and the use of cycle simulation to stress the logical design. The cycle simulation required new techniques to model equivalent behavior in order to verify the correct integration of nondigital components on the chip. Advanced methods were implemented to ensure correctness of the frequency-dependent design units and functionality across the asynchronous interfaces. A single verification environment was developed, providing the flexibility to seamlessly support the different levels of design abstraction and uncover the design errors at the appropriate level.

Introduction

The z990 eServer* I/O subsystem comprises an architecture providing I/O connectivity, networking connectivity, and intersystems connectivity. Since the introduction of the z900 system [1], significant improvements have been implemented in the I/O subsystem architecture. The higher I/O connectivity that is supplied breaks the limit of 256 channels, providing faster and more efficient transmission between systems and to the networking attachments. As depicted in Figure 1, an integral part of the new and improved z990 I/O subsystem is the STI switch chip.

The STI switch chip provides high-speed connections between the memory bus adapter (MBA) and the I/O attachments [2] and to other systems within the Parallel Sysplex* [3]. The switch chip is also called the multiplexor/demultiplexor chip. The connection to the MBA can be via the enhanced self-timed interface (eSTI), which is configured to operate at 2 GB/s, or via the multispeed self-timed interface (mSTl). The mSTI can be configured to operate at a data rate of 333, 500, or 1000 MB/s. This configuration dictates whether the switch chip operates as a level-one or as a cascaded level-two device. As a level-two device, the switch chip connects to a level-one STI switch via the mSTI link. This configuration provides higher connectivity. Four mSTI ports are implemented to support the downstream I/O connections.

The mSTI and eSTI support data is transferred via electrical cables in a serial fashion in which the clock is transmitted with the data across the physical link [4]. To support this interface, the switch chip integrates a physical adaptation layer and a logical adaptation layer for each of the interfaces. The physical adaptation layer serializes and deserializes the transfers of data, while the logical adaptation layer assembles the information packets and supports a parallel interface with the chip host logic.

The STI links and the supporting adaptation layers can be programmed to operate at multiple frequencies. In addition, the host logic integrates several clock domain units. In all, the switch chip integrates a total of seventeen different clock domains. As a result, the interfaces between these domains and link boundaries are asynchronous over a wide frequency range. Information-packet-forwarding logic algorithms were implemented to ensure arbitration fairness between incoming and outgoing packet flow and to optimize this flow as a function of data length and clock frequency.

To ensure a high-quality design and a fast time-to-market, the majority of the ASIC logic is verified using a functional cycle simulation environment. With 9.6 million transistors integrated in the switch chip, the objective was to utilize a high-performance cycle simulator [5] as much as possible where appropriate to maintain high performance across the various levels of simulation. The functional verification methodology [6, 7] implements a random biased approach to stimulate the designs with automated checking using cycle simulation.

Some of the logic units contain nondigital designs integrating analog components, differential interfaces, and subcycle wire delays. In this case, an event simulator is used to ensure the functional correctness of these components. Also, the approach is to verify these components in a standalone-unit environment so that these units need not be verified exhaustively at the chip level.

Register-transfer-level (RTL) design models are generated to verify the function within the chip as well as the internal and external interface protocols. This includes verifying the interactions between the new designs and the integrated intellectual property. These RTL models are referred to as one-cycle simulation models. In turn, full chip gate-level design models are created to verify the functionality and integration of error recovery, clocking structures, and test logic. Some of the error-recovery design features are verified using the partial RTL model.