Functional verification of a frequency-programmable switch chip with asynchronous clock sections

IBM Journal of Research and Development, May-Jul 2004 by Hoppe, B, Arthur-Mensah, B, Chencinski, E W, Joseph, S, Et al

Typical I/O ASIC designs have multiple clock partitions that are mostly asynchronous to one another; hence, special modeling must be applied to reflect an accurate relationship between the different clock sections and their numbers of simulator cycles per clock cycle of the respective domain. Algorithms must be applied to evaluate logic only in clock sections in which the clock edges actually occur.

Chip model stages

The logic design used in simulation was modeled under two main categories-one-cycle and two-cycle models. The following section describes the model stages used for the switch chip.

C models replaced the hardware design of the physical macros in the one-cycle logic design model. These models are referred to as mSTI and eSTI behaviorals in Figure 3. This allowed the simulation to mimic the actual mSTI link initialization sequence and information packet formatting, thus resulting in a shortened round-trip time for data transfer. Test cases that required the rigorous examination of packet forwarding between the STI logical macro and host logic were conducted under this abridged version of the switch design. A model implementing the behavior of the universal service interface (IF behavioral) is used to exercise base maintenance functions. Each clock domain is fed by a simulation-only programmable oscillator macro to allow frequency variation.

The two-cycle model, which is a full representation of the design of the switch gained from the gate-level netlist, underwent variations to accommodate pervasive function testing. This full chip gate-level model (also known as the two-cycle model), whose characteristics are augmented in subsequent versions, uses the service interface behavioral to set up the PLL, LBIST, logic reset, flush reset, and latch initialization logic. For a complete analysis of endto-end data transfer, additional mainline and recovery testing was performed on the full chip gate-level model shown in Figure 4. Each instance on an analog PLL was replaced by simulation-only logic (PLL behavioral) which was the equivalent of a real PLL in a cycle simulator. The content of this logic existed as described in [U]. It was used to verify the surrounding controls of the PLL to program the clock delay, pulse width, and frequency of the PLL.

To verify the correct function of the pervasive function required a multivalue representation of the logic, which led to the development of a multistate full chip gate-level cycle-simulation model. Apart from a binary zero or one, a value "X" can be assigned to every net to indicate not initialized or don't care. This first variant deployed an unknown initialization sequence on the design latches for additional testing of flush reset. Unlike the full chip gatelevel model, which required a 10% duty cycle for clocks, a second variant was developed to exhibit a 50% duty cycle for its clocks. The latter model was used for LBIST and signature matching verification. Asynchronous boundary testing utilized a third variant, shown in Figure 5, which incorporated additional simulation-specific random delay macros to provide simulation with programmable delays at critical asynchronous paths. This third model was periodically modified as the identification of asynchronous crossings within the design continued to evolve.