evolution of build-up package technology and its design challenges, The

IBM Journal of Research and Development, Jul-Sep 2005 by Blackshear, E D, Cases, M, Klink, E, Engle, S R, Et al

This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

Introduction

The increasing demand for computer performance has led to higher chip internal clock frequencies and parallelism, and has increased the need for higher bandwidth and lower latencies. Processor frequencies are predicted to reach 29 GHz by 2018, and off-chip signaling interface speeds are expected to exceed 56 Gb/s [1, 2]. Optimization of bandwidth, power, pin count, or number of wires and cost are the goals for high-speed interconnect design. The electrical performance of interconnects is restricted by noise and timing limitations of the silicon, package, board and cable.

As a result of rapidly emerging technologies and applications, the boundaries between semiconductor, packaging, and system technologies are no longer clear; they must all be considered concurrently in a system-level approach in order to optimize the substrate design. There is an increased awareness in the semiconductor industry that assembly and packaging is an essential and integral part of the semiconductor product. Packaging technology has become a critical competitive factor in many market segments, since it affects operating frequency, power, reliability, and cost.

Sequential build-up (SBU) laminate substrate technology is now the technology of choice for highdensity, high-performance silicon packaging. In 1997, SBU technology was selected by Intel [3] for flipchip packaging and has been widely adapted for this application. This paper reviews the invention of laminate substrate packaging and discusses rapidly evolving trends in the evolution of SBU, including its broadening application in IBM servers for high-speed system-level interconnects. The importance of properly designing the substrate for high-speed signaling is discussed, including identification of key parameters and design tradeoffs for both application-specific integrated circuit (ASIC) and microprocessor chip designs.

Applications place performance demands on packaging which can best be met by organic materials. The key attributes of organic laminate package technologies as they pertain to the electrical performance of the subassembly are highly electrically conductive metallurgy to minimize resistive voltage drops and to effectively deliver power to the chip; low-inductance connections to reduce simultaneous switching noise; low-dielectricconstant insulator materials to better match board impedances and to reduce undesirable parasitic capacitances; and advanced thermal interface materials to manage high power densities on the chip and to improve performance. The importance of properly designing the substrate for these applications is emphasized, including a discussion of the identification and control of key physical design parameters and a description of the design optimization technique.

History of technology development

Technology origins

Wire-bond interconnects have been the workhorse technology [4] for industry microprocessors and their associated supporting chips since the inception of the personal computer industry. Its primary advantages have been low cost, design flexibility, and thoroughly demonstrated reliability. Its major limitation is wiring capability in terms of both total numbers of signals and electrical performance.

Flip-chip interconnection has been a core IBM approach to silicon packaging [5] for much of the history of IBM servers. It provides the highest interconnect density from a chip to redistribution circuitry, or substrate, that is currently possible. Until recently, the interconnect density enabled by flip-chip technology could be provided only by multilayer ceramic substrates, which have a manufacturing cost significantly higher than that of other packaging circuit elements of a system, such as printed circuit boards (PCBs). Analysis of published design ground rules shows that build-up laminate substrate technology is a breakthrough approach to flipchip interconnection, achieving significantly higher perlayer wiring densities than printed circuit boards that use many of the same basic materials and processes. Build-up laminate cost is significantly less than that of ceramic dielectric-based competitive technologies. It offers electrical performance enhancements as well through the use of copper conductors and lower-dielectric-constant insulator materials.