evolution of build-up package technology and its design challenges, The

IBM Journal of Research and Development, Jul-Sep 2005 by Blackshear, E D, Cases, M, Klink, E, Engle, S R, Et al

Build-up layers

Build-up layers are characterized by copper trace dimensions such as width, thickness, and spacing. Almost all signal wiring in SBU occurs in build-up layers. Also important are dielectric characteristics, thickness, electrical properties such as dielectric constant and loss tangent, and thermal expansion characteristics. Dielectrics are silica-filled epoxies applied as dry films. Via characteristics are also critical. Drilling is through a single dielectric layer at a time; all vias in the build-up layers are blind and buried. Laser-formed vias are tapered, having different lower and upper diameters. The via land diameter is critical because it imposes boundaries on wiring capability and is an indication of the accuracy of the fabricator registration. Via size and pitch is an area of constant focus. Vias have traditionally been stairstepped, ascending through the build-up layers through the use of lozenge-shaped copper islands bearing the base of one via at one end and the drilled top of a via at the other. In stair-stepped vias, the plating thickness is approximately uniform as deposited both on sidewalls and base. Because stair-stepped vias impose a large blockage to wiring, the focus has been on development of stacked-via approaches. In stacked vias, the via is ideally filled with copper during plating, so that the metal surface at the via top is flat. The via for the next layer is placed with its base directly on the center of the one below. This structure offers significant wiring enhancement as well as enhanced heat transfer, but it is more rigid than the structure formed with stair-stepped vias and readily transfers stresses imposed by differential expansion. Thus, stacked vias are limited in the numbers of consecutive layers to which they can be applied, and are the subject of considerable development focus. At IBM, finite-element modeling is being used to identify necessary materials properties. Once appropriate materials are available, prototypes are fabricated and evaluated through thermal cycling. The ability to withstand 1,000 cycles between -55°C and 125°C is the criterion for success.

Core

The core is composed of glass-fiber-reinforced epoxy, jacketed in subtractively circuitized copper sheets. Most commonly, cores consist of a single dielectric layer, although multilayer cores may be used, formed by conventional laminated printed circuit board processing techniques. Where multilayer cores are used, added metal layers are typically used for power distribution rather than signal routing. Copper trace and space dimensions in the core have been significantly coarser than those in the build-up layers. Core vias are formed by mechanical drilling. In the past, the minimum drill size has been 200 µm, and minimum core via pitch with no circuit trace in the 400-µm range. To accommodate a circuit trace for maintenance of a power grid, minimum core via pitches in the 550-µm range have been the norm. Core vias are typically filled with particle-filled epoxy and then mechanically machined flat before build-up layer processing. This establishes the degree of flatness necessary for success in subsequent processes. Where micro-vias stacked over core vias are used, the core vias are plated shut. With C4 pitches at 200 µm easily accommodated by the wiring capability in the build-up layers, core via pitch has imposed a severe restriction on wiring capability. Thus, in essence, all wiring must be done in the top build-up layers of the substrate. The bottom build-up layers, although processed at the same cost and with the same techniques as the top, have been essentially vestigial, a processing artifact, their sole function being to connect the core vias to the module BGA pads. However, recent developments in mechanical drilling technology have produced a significant advance in core capability. Doubling of drill angular velocity permits drill sizes to be reduced to 100 µm for core thicknesses up to 400 µm with good resultant hole wall quality. This enables core via pitches adequate to fan out half of the signals through the core in the bottom buildup layers. It essentially doubles the wiring capability of a substrate at an incremental cost of more aggressive core ground rules. These fine-pitch cores are required only for applications of the highest complexity.