evolution of build-up package technology and its design challenges, The

IBM Journal of Research and Development, Jul-Sep 2005 by Blackshear, E D, Cases, M, Klink, E, Engle, S R, Et al

Typical materials, dimensions, and tolerances for an SBU laminate application are defined in Table 1. These values were used for the electrical analysis of the next section. The evolution of characteristic dimensions over time for build-up layers and cores is shown in Table 2. An overview of SBU technologies has been published [17]. In addition, for the following illustrative ASIC design case, the package pins can be classified in six groups: power, ground, serial embedded differential, source-synchronous single-ended, source-synchronous differential (which may be edge- or broadside-coupled, parallel or offset), and common clock single-ended (Figure 4).

Design challenges for ASIC applications

Emerging ASIC applications possess complex requirements for silicon, package, and end-user system design. Early engagement and interaction between the chip and package designers, and integration of their tools, are essential to addressing these requirements, improving design turnaround time, and making effective cost/ performance tradeoffs.

Chips can no longer be designed without knowledge of packaging capabilities. For example, package power grid design is becoming more demanding with low core voltages, which in turn places demands on the package to minimize the IR drops and effectively deliver power. Additional examples of ASIC device trends include signal isolation as well as C4 pitch reduction as a way to increase the usable wafer area, thereby reducing cost. Complexity can be added to the laminates by using more aggressive ground rules such as tighter via pitch, slacked vias, reduced line widths and spaces, and reduced core thicknesses. These trends ripple downstream to the module and assembly manufacturers. Advances are required in process and materials in order to handle thinner, larger carriers, and advances in thermal interface materials in order to manage the higher power densities.

General considerations

The key attributes of organic laminate package technologies as they pertain to the electrical performance of the module are the following: highly electrically conductive metallurgy to minimize IR drops and to effectively deliver power to the chip; low-inductance connections to reduce simultaneous switching noise; lowdielectric-constant insulator materials to better match board impedances and to reduce undesirable parasitic capacitances; and advanced thermal interface materials to manage high power densities on the chip and to improve performance. For high-speed applications, consideration must be given to simultaneous switching noise, electrical coupling noise, signal trace resistance, low dielectric loss, and signal trace characteristic impedance. Depending on the off-chip signaling technique used for the various interfaces on the chip, either near-end or far-end crosstalk noise is a concern. For instance, near-end crosstalk noise is important for full-duplex serial links in which the transmit and receive macros are placed on the chip close to each other because of the sensitivity of the received attenuated signal to coupled noise. Similarly, simultaneous bidirectional signaling is very sensitive to near-end noise as well as to impedance mismatches between the substrate and the board [18]. Therefore, this type of interface requires a controlled-impedance environment, preferably close to the impedance of the transmission link, with low crosstalk and low resistance.