Space System Health Management and Microelectronics

Logistics Spectrum, Jan-Mar 2005 by Blackburn, Tiana

Self-contained spare components, built-in testing and internal program reconfiguration are now as real as the sparkle in someone's eyes 17 years ago. On-chip redundancy to enable the chip to identify its faults, bypass failed parts and form new interconnections to incorporate spare devices - all without human intervention - are now possible.

Pratt & Whitney Rocketdyne (PWR), an International Space Station (ISS) original equipment manufacturer in Canoga Park, California, processes a small number of repairs for the electrical power system (EPS) orbital replaceable units (ORUs). United Space Alliance provided logistics system integration for the entire ISS. From these perspectives we will approach conceptual solutions to system health management. This article will discuss very high speed integrated circuit (VHSIC) technology and the use of application specific integrated circuits (ASICs), as well as recent IC failures and electrically erasable programmable read-only memory (EEPROM) in-situ maintenance onorbit.

The term VHSIC is a somewhat outdated term, as is small scale integration, medium scale integration and large scale integration, although very large scale integrated circuits are one type of ASIC used in all ISS EPS ORUs. The idea behind VHSIC was to create a device that would do multiple tasks so that ASIC development could be minimized. The main reason the VHSIC is outdated is that "very high speed" is a term whose definition moves with time. We now describe the device's function rather than its speed capability.

Today a relatively new term is being used called system on a chip (SOC). This device has a processor, memory management, PROM and random access memory all on the same chip. Because they are monolithic (formed from a slice of a single crystal) the processing speed for these systems is increased at least five times. If system requirements had remained the same, then the VHSIC term might have survived, but at present the data processing that is required on Space Station hardware is relatively slow and it has not required the use of VHSIC.

Microprocessors designed for EPS ORUs were imbedded on common controller circuit cards that were located in multiple ORUs. The microprocessor is "...part of an ASIC design which utilizes a proven, radiation-hardened gate array... Gate array parts are manufactured up to the final two metal layers required to interconnect gates that make up the circuit design. These gate array blanks are then stockpiled on the shelf until needed." Later these parts were upgraded by screening tests, and inprocess tests were added to meet requirements. "In the final steps, the interconnecting metal layers, passivation, packaging and testing are added to produce a finished part. The part is then characterized electrically and qualified to an "S" level (space rated) as a gate array blank by testing a reference design. The finished part then only needs to be tested to determine the characteristics which are affected by the last steps in the process."1

The common controller circuit card was successful in several different applications within the power management and distribution system. Requirements of ORU assemblies are diverse. For example, the sequential shunt units regulate solar power to primary power buses, the battery charge discharge units regulate the battery charge and discharge rates, and the pump flow control system monitors and controls pumps circulating fluid in the radiators of the ISS thermal control system. "To achieve this kind of flexibility, the common controller circuit design uses a programmable, embedded microprocessor which allows the transfer of many functional requirements to firmware. This feature allows parallel effort in hardware and firmware design. The parallel effort required coordination between firmware development engineers, system design engineering, ORU test engineers and system test engineers, among others."1 Programmable logic enables the same microprocessor the flexibility to be used for multiple ORUs with different functions.

On future designs, major coordination will also be required when functions are shared between subsystems. Interplay between reconfigurable modules with self-test and self-repair features will require major coordination to configure, program and debug.

An ASIC is definitely faster than a more general type device when performing these functions, but with the cost and schedule risk of ASIC development and with the faster processors, it makes more sense today to use generic devices such as reduced instruction set chip processors, digital signal processor, field programmable gate array and SOCs in most applications.1

That being said, NASA has been looking into reconfiguring ASICs for space applications. The reconfigurable ASICs that offer real time compensation for faults will be in the system trade space when the next advanced space electronics system is designed. It will, in effect, change maintenance into something more often planned rather than unscheduled. The goal is to have systems reconfigure much like a hard drive does on the computer and then provide a status as to when the risk is getting high and it is time to repair/replace the faulty parts.2