GaAs-Based Metal-Oxide Semiconductor Field-Effect Transistors with Al^sub 2^O^sub 3^ Gate Dielectrics Grown by Atomic Layer Deposition

Journal of Electronic Materials, Aug 2004 by Ye, P D, Wilk, G D, Yang, B, Kwo, J, Et al

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al^sub 2^O^sub 3^ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al^sub 2^O^sub 3^ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f^sub T^) of 14 GHz and a maximum oscillation frequency (f^sub max^) of 25.2 GHz have been achieved from a 0.65-�m gate-length device. The interface trap density (D^sub it^) of Al^sub 2^O^sub 3^/GaAs is evaluated by the hysteresis of drain-source current, I^sub ds^, versus gate-source bias, V^sub gs^, and the frequency dispersion of transconductance, g^sub m^.

Key words: Depletion mode, GaAs metal-oxide semiconductor field-effect transistor (MOSFET), atomic layer deposition (ALD)

INTRODUCTION

The GaAs-based, metal-oxide semiconductor fieldeffect transistors (MOSFETs) have been a subject of study for several decades.1-10 The GaAs-based devices potentially have great advantages over Si-based devices for high-speed and high-power applications, in part, from an electron mobility in GaAs that is ~5� greater than that in Si, the availability of semi-insulating GaAs substrates, and a higher breakdown field. Currently, the GaAs metalsemiconductor field-effect transistor (MESFET) is the dominant device for high-speed and microwave circuits. The MESFETs feature gates formed by metal-semiconductor (Schottky-barrier) junctions while MOSFETs have oxide layers (higher barrier) between metals and semiconductors. Compared to GaAs MESFETs, GaAs MOSFETs feature a larger maximum drain current, much lower gate-leakage current, a better noise margin, and much greater flexibility in digital integrated-circuit design because of large gate-voltage range. The main obstacle to GaAs-based MOSFET devices is the lack of high-quality, thermodynamically stable insulators on GaAs as a gate dielectric that can match the device criteria similar to SiO^sub 2^ on Si. Both GaAsbased native oxides and deposited insulating layers have been attempted as gate dielectrics. After decades of efforts on forming an amorphous oxide on a III-V compound semiconductor, much progress has been made recently,11-14 e.g., atomic layer deposition (ALD)-grown Al^sub 2^O^sub 3^ on III-V semiconductors,15,16 a marriage of Si technology to the III-V compound semiconductor field.

To achieve higher transconductance as well as to downsize the device for higher integrated density, the reduction of the gate oxide thickness is critical. A gate material with a much wider bandgap, providing a higher potential barrier with GaAs, is able to significantly reduce the gate-leakage current for the same layer thickness of other materials. The Al^sub 2^O^sub 3^ is a highly desirable gate dielectric with a high bandgap of ~9 eV, which is much higher than other feasible gate oxides, e.g., Ga^sub 2^O^sub 3^ with a bandgap of ~2.45 eV. As a popular high-[kappa] gate oxide, Al^sub 2^O^sub 3^ has a dielectric constant as high as 8.6-10, compared to 3.9 for SiO^sub 2^. The Al^sub 2^O^sub 3^ is a highly desirable gate dielectric not only because it has high bandgap, but also, it has a high breakdown field (5-10 MV/cm) and high thermal stability (up to at least 1,000�C), and remains amorphous under typical processing conditions of interest. It is easily wet-etched yet is robust against interfacial reactions and moisture absorption (i.e., nonhygroscopic). The ALD itself is an ex-situ, robust manufacturing process that is already commonly used for high-[kappa] gate dielectrics in Si complementary metal-oxide semiconductor technology7 .17 It does not require ultrahigh vacuum conditions for wafer transfer between semiconductor epilayer growth and oxide layer deposition and may soon find wide applications in microelectronics.

In this paper, we demonstrate GaAs-based MOSFETs with excellent performance using an Al^sub 2^O^sub 3^ gate dielectric grown by ALD. These MOSFET devices exhibit negligible drain-current drift and hysteresis, extremely low gate leakage, high transconductance, and good radio-frequency (RF) characteristics. Through transistor characteristics and modeling, such as drain-current hysteresis and transconductance-frequency dependence, we evaluate the interface trap density (D^sub it^) of ALD-grown Al^sub 2^O^sub 3^ on GaAs at the device level.

EXPERIMENT

A schematic diagram of the depletion-mode GaAs device is shown in Fig. 1a. A 1,500-[Angstrom], undoped GaAs buffer layer and a 700-[Angstrom], Si-doped GaAs layer (4 � 10^sup 17^/cm^sup 3^) were subsequently grown by molecular beam epitaxy on a (lOO)-oriented semi-insulating 2-in. GaAs substrate. After the semiconductor epilayer growth, the wafer was transferred ex situ to an ASM Pulsar20000(TM) ALD module. The GaAs MOSFET devices employed an Al^sub 2^O^sub 3^ gate dielectric of thicknesses ranging from 80 [Angstrom] to 500 [Angstrom]. The Al^sub 2^O^sub 3^ oxide layer was deposited at a substrate temperature of 300�C, using alternatively pulsed chemical precursors of A1(CH^sub 3^)^sub 3^ (the AL precursor) and H2O (the oxygen precursor) in a carrier N^sub 2^ gas flow. Each precursor undergoes a self-limiting reaction at the surface, and the Al^sub 2^O^sub 3^ film is, thereby, grown with excellent thickness and uniformity precision. A highresolution transmission-electron microscopy image illustrates the abrupt interface.16 all wafers were transferred in air before and after ALD growth with no requirement for ultrahigh vacuum conditions. A post-deposition anneal was done at 600�C for 60 sec in an oxygen ambient. Device isolation was achieved by oxygen implantation. Activation annealing was performed at 450�C in a helium gas ambient. Using a wet etch in diluted HF, the oxide on the source and drain regions was removed while the gate area was protected by photoresist. Ohmic contacts were formed by electron-beam deposition of Au/Ge/Au/Ni/Au and a lift-off process, followed by a 425�C anneal in a forming-gas ambient. Finally, conventional Ti/Au metals were e-beam evaporated, followed by lift-off to form the gate electrodes. The process requires four levels of lithography (alignment, isolation, ohmic, and gate), all done using a contact printer. The source-to-gate and the drain-to-gate spacings are -0.75 �m. The sheet resistance of the source/drain region outside the gate and its contact resistance are measured to be 1.3 kohm/sq and 1.5 ohm-mm. The gate lengths of the measured devices are 0.65 �m, 0.85 �m, 1 �m, 2 �m, 4 �m, 8 �m, 20 �m, and 40 �m.