Calibration of Electromigration Reliability of Flip-Chip Packages by Electrothermal Coupling Analysis

Journal of Electronic Materials, May 2006 by Lai, Yi-Shao, Kao, Chin-Li

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black's equation to calibrate the experimental electromigration fatigue lives.

Key words: Electromigration, reliability, electrothermal coupling analysis, Black's equation

INTRODUCTION

Electromigration is responsible for structural damage of metallic conductors as a result of atomic diffusions driven by high electric current density.1 This phenomenon relates greatly to the current density and temperature carried by a metallic conductor. For a flip-chip package, because of the differences in feature sizes and electric resistivities between a solder bump and its adjacent traces, current densities around the regions where traces connect the solder bump increase significantly, which accelerate depletion of the solder bump due to the increase of momentum of electron charges around these regions. Inside the solder bump, the temperature increases as a result of resistance to the electric current flowing through the solder bump. The temperature increase activates the atoms and hence lowers the momentum required to move them. The mutual interactions of current crowding and Joule heating hence accelerate electromigration failures of the solder bumps.

Electromigration is particularly important for a contemporary flip-chip package due to demands to increase the electric current carried by its solder interconnects while decreasing their sizes. Diffusionrelated failure mechanisms have been observed, in particular when flip-chip solder interconnects are subjected to high electric current at high ambient temperatures (e.g., Refs. 1-9). Understanding the electromigration reliability of flip-chip solder interconnects and corresponding morphology and failure mechanisms has become a consequential topic in an industry that desires a reliable electronic package design.

In this study, three-dimensional electrothermal coupling analysis (EGA) is employed to examine and quantify effects of current crowding and Joule heating in a flip-chip package that has constant electric currents applied to a daisy-chained circuit of solder bumps. The calculated current crowding and Joule heating effects are integrated in Black's equation to calibrate the experimental electromigration fatigue lives.

ELECTROMIGRATION EXPERIMENTS

The test vehicle applied in this study is a 27 × 27 × 1.14 mm^sup 3^ flip-chip package, which involves a 7.62 × 7.62 × 0.74 mm^sup 3^ silicon die interconnected to a 0.3-mm-thick two-layer substrate with 720 non-solder-mask-defined solder bumps. The pitch of the solder bumps is 270 µm. The diameter and stand-off of a solder bump are 140 µm and 100 µm, respectively. The surface finish on the Cu pad of the substrate is electroless plated Ni/Au, with a Ni thickness of 5 µm and a Au thickness of 0.05 µm. The diameter of the trilayer Al/Ni(V)/Cu underbump metallurgy (UBM) is 110 µm, while the thickness is 3 µm in total. The silicon nitride passivation is 1.5 µm thick, and its opening is 90 µm. The Al trace on the die is 65 µm wide and 1 µm thick, while the Cu trace on the substrate is 65 µm wide and 15 µm thick. The diameter of the Al pad is 140 µm. The solder-mask opening is 110 µm.

Figure 1 shows the layout of circuits and bumps on the flip-chip test vehicle. Only a single daisy chain at the edge of the die on the encompassed region shown in Fig. 1 is electrified with a constant electric current, I. Figure 2 shows the configuration of this particular electrified daisy chain and directions of current and electron charge flow, which are opposite to each other. Notice that on bumps Vl and V2 , electron charges flow from the UBM to the substrate while on bumps V1- and V3- the charges flow from the substrate to the UBM. The current bypasses the V2-/V3 bump. Specimens are placed in a furnace to control the ambient temperature, T^sub amb^. Electrical resistances on three sections on the particular daisy chain, labeled R^sub 1^, R^sub 2^, and R^sub 3^, are monitored in situ during the test. Failure is defined as the resistance of one of the three sections exceeding 2 ohm.4,7-9 The resistance of the section labeled R^sub 4^ is also monitored to calibrate the resistivity of the Cu trace.10 Note that R^sub 1^ involves a section of the Al trace of a resistance of R^sub c^ and two solder bumps, whose resistances are R^sub a^, for which electron charges flow the UBM to the substrate, and R^sub b^, for which electron charges flow from the substR^sub a^te to the UBM; R^sub 2^ involves a section of the Al tR^sub a^ce of a resistance of R^sub c^ and a solder bump of a resistance of R^sub a^; R^sub 3^ involves a section of the Al tR^sub a^ce of a resistance of R^sub d^ and a solder bump of a resistance of R^sub b^; R^sub 4^ represents the resistance of a section of the Cu trace. On the basis of the assumption that R^sub d^ = 4R^sub c^ regaR^sub d^ing the lengths of the two sections of Al traces, we have R^sub 1^ = R^sub a^ R^sub b^ R^sub c^, R^sub 2^ = R^sub a^ R^sub c^, and R^sub 3^ = R^sub b^ 4R^sub c^, or R^sub a^ = (R^sub 1^ 3R^sub 2^ - R^sub 3^)/4, R^sub b^ = R^sub 1^ - R^sub 2^, and R^sub c^ = (-R^sub 1^ R^sub 2^ R^sub 3^)/4.8