Experiments on VME and ISA buses for a computer architecture laboratory

International Journal of Electrical Engineering Education, Apr 2001 by Moreno, L, Gonzalez, E J, Pineiro, J D, Estevez, J I, Et al

Abstract This article presents a set of hardware experiments in the area of computer architecture. They combine their practical aspects with a set of simulation exercises.

We propose a series of practical applications including both asynchronous VME/synchronous VME/synchronous ISA buses and parallelism. The system on which experiments are carried out is an 80 x 86 CPU-based prototype.

Keywords: hardware: 80 X 86-based prototype; buses

Introduction

Teaching in practical subjects, such as electronic engineering and computer science, should be an appropriate combination of theory, exercises and laboratory experimentation.1-4 With regard to the practical part, a number of simulation packages that provide suitable learning environments have appeared this past decade. In the particular case of computer architecture teaching, there are excellent simulation packages like SPIM,5 WinDLX, Midas,6 DLXVSim,7 etc. that facilitate practical instruction in especially important areas such as efficiency of particular instruction sets, application of segmentation techniques, memory management or analysis of structural improvements like the addition of new functional units, cache memories or out-of-order execution.

However, this option is not complete and should be combined with real laboratory experience. It is not easy to create a balance between both types of experiences. Simulation experiences are often used because they are easier and cheaper, and teachers do not need to supervise the work of the students as closely as in hardware instruction. In contrast, hardware experimental procedures take a long time, and they may be tedious and too difficult when they are not appropriately designed. Nevertheless, it is well known that there are many areas that can not be shown through simulation. These practical aspects can only be learnt through carefully chosen hardware experimentation.

Students can obtain a deeper understanding of parallelism-related issues in bus-based networks through hardware experiences, such as arbiter designs, shared memories, critical area access, etc. A design that involves parallelism forces students to

be careful with the design

formulate debugging strategies

use appropriate display tools.

The aim of this article is to present a number of hardware procedures that are designed for the VME/VXI bus. We think that the proposed set of laboratory excercises satisifies the previous requirements.

Description of the prototype and related tools

The set of practical exercises suggested in this article is based on a prototype that has been fully designed at our laboratory. Use of commercial systems based on the VME bus, such as the MiniForce system (where students carry out Motorola 68000 assembler language procedures), has been discarded. Initially, the prototypes that are designed by the students have several critical failures (short-circuits between the supply and the ground, for example, or just non-precautions - like turning off the system when the prototypes are being connected to or disconnected from it). Consistently, when those prototypes are directly connected to the bus of the MiniForce system, they are likely to break some of the components the system is made of (CPU, interfaces, etc.).

The designed prototype, manuals for which are available in the laboratory, is based on an Intel 80 x 86 processor, and its main components are:

Intel processor

Local memory

Hexadecimal keyboard controllers, display with 7 segment leds

ISA bus subset (synchrnous bus)

VME adapter interface (VME bus subset)

ROM monitor program: keyboard control, display, debugging...

Programmable Peripherical Interface (PPI) as general purpose input/ output device.

The microprocessor runs in minimum mode, because there are few elements in the system. In this mode, the CPU generates all necessary system control signals.

The prototype scheme is shown in Fig. 1. In it, reset and crystal circuits manage the system timer (8254) whereas a signal from this timer governs the microprocessor clock. Addresses (AO-A19), through a simple decoder circuit, and data (DO-1315) signals are connected to memory chips.

There are two kinds of memories. The first one is an EPROM 2732-A. The monitor program, the set of interrupt vectors, and room for future implementations are located in this unit, between FE00:0000 and FE00: FFFF addresses. The second one is a RAM 43256. This unit comprises the monitor program data area, the user program memory area and the stack memory area that are located between 0000:0000 and 0000:FFFF addresses.

The eight least significant bits of the data bus are connected through a programmable keyboard/display interface INTEL 8279-5, to keyboard and display units (in this implementation, both are hexadecimal).

The required signals are connected to a simplified VME adapter interface (details will be shown below). This interface is connected to the system output through an expansion connector.

Prototype characteristics are:

Universality: It makes static/dynamic memory extensions through both of the synchronous (ISA bus) and asynchronous (VME bus) buses possible. Simplicity: With prototypes like this one, students do not damage commercial systems, repairs of which can be complex and expensive.