Experiments on VME and ISA buses for a computer architecture laboratory

International Journal of Electrical Engineering Education, Apr 2001 by Moreno, L, Gonzalez, E J, Pineiro, J D, Estevez, J I, Et al

Another aspect, and perhaps the most pedagogical one, is that the implemented design complies with VME protocol time specifications. This circumstance can be checked with the logic analyser.

When DS* signals are both high, DTACK* (driven by the slave) is high too. But, when at least one DS* signal is driven low by the master, the slave answers by driving DTACK* low after a minimum time, given by a VME specification."1 This is guaranteed by including a delay line. Finally, when the master drives DS signals high again, DTACK* is driven high almost immediately.

Students can conveniently develop this procedure with the logic analyser, as measurement problems are greatly reduced (protocol times can be measured in a precise way).

Slave being shared by 2 masters

Once the previous procedure has been completed, the next logical step is that of designing a system with several masters that access a common resource. The way in which the interface has been designed makes this experiment very simple. Students only connect the new master to the implemented bus, as the arbitration has been previously implemented.

However, the most interesting aspect of this procedure is not the connection itself, but the aspects related to the parallel processing. In order to work with these concepts, a producer/consumer problem is proposed as an exercise. Students carry out this procedure via the designed hardware, defining access to a critical area through a binary semaphore. In this way, students can check asynchronous bus advantages, controlling bus control lines (signals related to arbitration: BBSY*, BR*, BG* and BCLEAR*) and checking, for example, whether data written on the common resource is correctly read.

Design and implementation of arbitration devices

This experimental procedure is useful, because arbitration time specifications have to be considered together with previous requirements.

A previous arbiter design can be given to the students or in case some students want to get better marks, they can design a new arbiter themselves that could be based on other arbitration policies.

On this point, we will consider the example of a system of two masters. If the master that is not in control of the DTB requests its use, it drives its BR* signal low. The arbiter grants control of the DTB to the master through the BGxIN* signal, then the master drives its BBSY* signal low and starts its transfer cycle(s). Finally, the master releases the DTB driving its BBSY* signal high.

The chosen design has several feedback signals, whose function is to avoid two masters accessing the slave simultaneously. If the design is thoroughly analysed, it can be shown that it can be simplified slightly. However the redundant sections have been left, giving more robustness to the design.

Time diagram interpretation (acquired knowledge test)

Once students have completed the previously described procedures, they are shown several chronograms captured with the logic analyser, where the different steps of the protocols are emphasised. Students have to interpret them correctly showing whether chronograms comply with VME bus specifications or not. These time diagrams are shown in ascending order of complexity (one master-- two masters).