Experiments on VME and ISA buses for a computer architecture laboratory

International Journal of Electrical Engineering Education, Apr 2001 by Moreno, L, Gonzalez, E J, Pineiro, J D, Estevez, J I, Et al

Later, students are evaluated once again, but this time tested individually in their final exam. A full chronogram appraisal procedure, which is applied for the purpose of checking student knowledge suitably, will be used.

Conclusions

A series of experimental procedures based on synchronous and asynchronous buses is proposed. These practical exercises allow computer architecture students to gain valuable experience in hardware designing, debugging and operating specialised instrumentation (logic analyser). In this way, their previous knowledge acquired through the theoretical lectures and simulation experiments is tested and improved in a laboratory.

Acknowledgments

The authors of this paper wish to thank students who have taken part in the development of the experimental prototypes, especially Ram6n Lopez Frias and Jose Javier Cabrera Lopez, and their tutors, Dr Alberto F. Hamilton Castro and Juan Julian Merino Rubio. We also wish to thank Roberto Betancor Bonilla for his work in the development of the interfaces.

References

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L Moreno, E. J. Gonzalez, J. D. Pineiro, J. I. Estevez, J. J. Merino, J. F. Sigut and R. M. Aguilar

Department of Applied Physics, University of La Laguna, Tenerife, Spain

E-mail {lorenzo, evelio, jd, nacho, merino, sigut rosi}@cyc.dfis.ull.es