Large-scale, parallel embedded applications: A hardware design model for software engineers

International Journal of Electrical Engineering Education, Oct 2001 by Fleury, M, Self, R P, Downton, A C

Large-scale, parallel embedded applications: a hardware design model for software engineers^

Abstract Parallel servers are becoming an important sector in the embedded systems marketplace. If software engineers are to implement the multi-algorithm applications that these servers support, then educators should provide clear design routes which inculcate system-level thinking. Pipelined Processor Farms (PPF) is one such topdown design strategy. The contemporary hardware diversity within both processor- and instruction-level parallellism requires incorporation of a coprocessor model at the node or sub-system layer. Two suitable software-based approaches are reviewed: one which maintains the traditional aspects of hardware modeling, SystemC, and the other, Handel-C, which introduces silicon compilation to the CAD laboratory.

Keywords parallelism; top-down design; hardware/software codesign; silicon compilation

Developments in the electronic engineering industry require continual updating of university degree courses without merely feeding transitory demands or neglecting enduring principles of design. Presently, thin-client devices, such as PDAs (personal digital assistants) and WAP (Wireless Application Protocol) ,phones, are proliferating in the market place and may eventually far outstrip the volume of conventional PCs. With every thin-client device, a fat server is needed to provide the services which provide product differentiation. The server supports large-scale, embedded applications but is required to give real-time responses, necessitating a parallel architecture.

For example, database enquiries on a mobile 'phone may soon require large-- vocabulary speaker-independent continuous speech-recognition servers, as an alternative to conventional call centres. Processor-level parallelism can reduce enquiry latency, and provide sufficient throughput to cope with many simultaneous callers. There may also be a requirement for finer-grained parallelism, where, for example, Viterbi recognition network searches can utilize the streaming SIMD (Single Instruction Multiple Data Stream) instruction sub-set on Intel processors.1

To compete in this market, companies must cope not only with product lifetimes that can now be shorter than six months, but also with a shortage of software engineers trained for embedded systems; and, more chronically, engineers able to cope with fine-grained parallelism, which requires a hardware orientation. The former implies a streamlined design process, while the latter implies a training programme for graduate engineers.

At present, many companies within the electronics industry have a shortterm strategy of competing for a diminishing supply of hardware-trained graduates with financial inducements, leading to spiraling wage bills. This supply problem is likely to be exacerbated in the short and medium term by the strong preference in the UK (by a ratio of approximately 7: 1 2) that university applicants show for computer science rather than electronic engineering degree courses. Not only is the supply of hardware-trained graduates strictly limited (about 3,000 admissions to electronics courses per year^), but there is a growing fondness for a predominantly software outlook to design. This is evident in the current interest in hardware/software co-design for systems-on-a-chip, and for CIC rather than HDL (hardware design language) modeling of hardware. For example, the design of the Neon 256-bit 3D Graphics Accelerator3 employed C templates for bit-width specification, 'C' mathematical libraries, and a fast cycle-accurate simulator written in 'C'. A C-to-Verilog translator enabled hardware synthesis to take place.

Therefore, an obvious question arises: how can universities address the shortfall in electronic engineering personnel equipped to produce hardware/ software co-designs and implementations? This paper suggests:

* a generic, top-down design methodology capable of looking at applications as systems;

* a way of accommodating processor-level and instruction level parallelism within the system; and

* a seamless way to pass from high-level design to implementation.

Moreover, the whole should offer clear guidance to the novice hardware designer, and accord with the current software-based orientation. Our attack is two-pronged: (1) an existing top-down design methodology is extended to encompass instruction-level parallelism, and (2) the hardware-specific level of design is removed, in some measure, by means of hardware or silicon compilation.

Background

Top-down design methodology

A system design methodology should offer novice hardware engineers a clearly signposted path from a complex application programmed within an overspecified, sequential model of computation to a performance-oriented parallel design. Guidelines for top-level partitioning of the system should be available, together with examples of the system design methodology in action, ideally in a web-based format in the manner of the CalTech Archetypes project4 for parallel applications. It is also important to include examples of where a methodology cannot be applied. The Pipelined Processor Farm (PPF) methodology5 has been applied to a variety of contemporary applications in the fields of vision, pattern recognition, and signal processing. It has also been taught in undergraduate courses as a way to estimate pipeline traversal latency, throughput, and scalability, based on profiling statistics obtained from sequential code.