Large-scale, parallel embedded applications: A hardware design model for software engineers

International Journal of Electrical Engineering Education, Oct 2001 by Fleury, M, Self, R P, Downton, A C

Though the design flows of Figs. 11 and 12 have a superficial resemblance, in fact the superstructure provided by SystemC is more aligned to behavioural modeling stage in an HDL. A sign of the emphasis on modeling is that the simulator in SystemC is integrated with the binaries, thus improving simulation speed. Iterating through implementation refinement in Handel-C involves re-coding a 'C' program in order to reduce the number of cycles. It is only when the code is transferred to the FPGA, that it becomes apparent that the clock width may also need to be reduced. However, increasingly due to short product lifetimes, the need to refine or 'tweak' VHDL is also less pressing. Note also that it is perfectly possible to arrange for VHDL output from Handel-C.

The refinement process in both SystemC and Handel-C currently continues to require a design expert as knowledge of how to improve the hardware/code resides in the designer.

Hardware compilation with SystemC

SystemC is an industry-led de facto standard, which addresses the need for multi-vendor tool inter-operability. The founding members of the consortium have each contributed expertise (intellectual property) in the form of class libraries, as follows:

* Synopsis: 'Scenic' modeling environment;

* CoWare: module interface abstraction technology;

* Frontier Design: fixed-point data-type mapping. The class libraries and simulator are supplied on a no-fee basis.

Both System-C and Handel-C have been applied to coding a simple counter circuit, Fig. 13.17

The SystemC version of the code is given in Fig. 14. It will be seen that the nomenclature and conceptual model of HDLs such as VHDL and Verilog has been preserved in SystemC. For example, SystemC has modules, ports, signals, and clocks. In the figure, the module macro is simply expanded to a C struct (a class with no private members). C template classes allow ports to be parameterized by data-type. Within the main control section (not shown), signals and clocks linking the ports of modules are similarly instantiated. In the figure, a process is created through a C constructor, through the SC_CTOR macro. Associated with the process is a sensitivity list, as in VHDL, the definition being inherited from an sc module superclass. Therefore, processes are registered with the SystemC kernel (linked in later), and are activated whenever an event, such as a positive clock edge, triggers it. In terms of modeling concurrency, SystemC also provides thread processes which are implemented as co-routines (self-scheduling processes40), which conveniently avoids having to create a separate method for each state of a module. A thread continually executes unless it suspends itself or passes control to another thread.

SystemC can be employed to model a variety of hardware behaviour. For example, a clocked thread is associated with a clock which steps the thread through the actions of a finite state machine. Clocked threads can model bus behaviour. SystemC clocks, specified in terms of time units, duty cycle, and start-up settings, can be applied (within testbenches) to regions of a circuit.