Large-scale, parallel embedded applications: A hardware design model for software engineers

International Journal of Electrical Engineering Education, Oct 2001 by Fleury, M, Self, R P, Downton, A C

Fortunately, CAD tool developers have moved towards making the `lookand-feel' of modeling tools more 'C'-like and less HDL-like. Below the outward appearance, educators are presented with a choice: SystemC hardware compilation models concurrency by coroutines, interprocess communication by signals, and hardware timing by local clocks, much within the conceptual framework familiar to VHDL or Verilog-trained engineers; while Handel-C models concurrency by cobegin blocks, interprocess communication by channels, and hardware timing by a local clock, in a manner familiar to parallel programmers of Occam and the transputer. Handel-C does not model hardware as such, but presents (through silicon compilation) a software model to hardware. Alternatively, Handel-C can be compared to Java, though rather than the Java Virtual Machine, we have the synchronous Occam virtual machine.

The simplicity of the Handel-C virtual machine may, like Occam before it, limit Handel-C's applicability, whereas SystemC is suitable for modeling ASICs. For educators, this is probably not a significant disadvantage as FPGAs are commonly employed to model other digital architectures. One practical consideration is that Handel-C provides a `one-stop' solution, whereas SystemC is dependent on forthcoming third-party hardware synthesis tools. If the objective is to train software-oriented engineers to participate in the application system design process then Handel-C does indeed abstract away from the hardware, which should increase its acceptability to computer science students.

Acknowledgement

This work is being carried out with assistance from an EPSRC/DERA CASE studentship no. 9930329X.

^ A preliminary verson of this paper was presented in the form of two talks at the EEUG workshop 2000.

* Figures are averaged over the last three years.

^ There are also plans by Miron Inc. to revive the earlier SIMD DAP coprocessor as a sing chip with embedded DRAM.

' FPGAs are also included in the undergraduate computer engineering curriculum" as a means of prototyping ASICs, in a way that mimics Intel and AMD usage. Low-cost boards are employed such as the Altera UPI student CPLD board or Xilinx's XS40 and XS95, or custom boards.?5 There is an educational board with the Xilinx Virtex FPGA intended for laboratory usage. Handel-C is suited to this purpose.

I VHDL had its origin as a hardware documentation language, hence the often-heard accusation of verbosity. It is also possible to compare VHDL to C/C as a programming language, divorced from the issue of how well hardware is modeled. but this comparison is pursued elsewhere."

' Celoxica Ltd. formerly traded as Embedded Solutions Ltd.

References

I A. C. Valles, Using Streaming SIMD Extensions to Boost Speech Recognition Performance. Technical report (Intel Inc., 2000). Available at http://developer.intel.com/update/archive/I issue 19/stories/ssl.htm.

2 Universities and Colleges Admissions Service (UCAS), Summary Statistics for 1997-1999. Technical report (2000). Figures available from http://www.ucas.com/figures/archive/ download/index.html.