A virtual interactive teaching environment using XML and augmented reality

International Journal of Electrical Engineering Education, Oct 2001 by White, Martin, Jay, Emmanuel, Liarokapis, Fotis, Kostakis, Costas, Lister, Paul

Abstract We present a new approach to the teaching of top-down design of VHDL using a novel virtual interactive teaching environment. This environment enables students to learn more effectively using virtual multimedia content while exploiting XML, and augmented reality. This environment can be adapted for teaching of other subject areas.

Keywords augmented reality; electronic design automation; VHDL; virtual environments; XML

At Sussex, in the School of Engineering and Information Technology, we teach top-down design with VHDL to the 4th year MEng Electronics and Computer Systems majors on a course called Integrated Circuit, Design 2 (ICD2) - our Integrated Circuit Design 1 being the VLSI Systems full custom course using ChipWise. We also teach it on our MSc in Digital Electronics as half of the VLSI ASIC Design Module - the other half again covers full custom design, but with L-EDIT. On the ICD2 course we use industry leading electronic design automation (EDA) tools. The EDA tools we use are ModelSim from Model Technology, which is used for simulation, Synplify from Synplicity, which is used for synthesis, etc. and Max plus II from Altera, which is used for placing and routing the Altera FPGAs. We are also evaluating Renoir from Mentor Graphics to allow graphical design entry in our chosen top-down design flow.

Our teaching of top-down design with VHDL is delivered through seminars and laboratories focused on a self-based learning approach using multimedia tools from Esperan.1 This paper presents a new teaching and learning virtual environment called VITE that uses XML and augmented reality to enhance our current teaching and learning model. Using VITE students can visualise principles and test their learning in virtual scenarios.

Our current teaching model

Our current teaching model is illustrated in Fig. 1, and is based around delivering:

* a 3-hour interactive seminar to introduce students to the course;

* a 1-hour demonstration of EDA tools including the specific design flow used;

* 11 to 12 hours completing the Esperan Multimedia HDL tutorials: there are 10 laboratory exercises included in the tutorials;

* 15 hours completing the design exercise, which is assessed: students have to submit a 4000-word report inclusive of diagrams and results, and a short essay.

The core of our teaching model is focused on a self-based learning approach using the Esperan MasterClass tutorial. We feel this is appropriate for several reasons. First, the class is small, approximately 10 students. Second, the students are 4th year MEng level and capable of self-direction to a large extent. Third, because the class is small and predominantly laboratory based the teacher and laboratory demonstrators can interact on an almost one-to-one basis in support. The reader should note that although the class is small we still insist on two demonstrators and a teacher during the laboratories because the EDA tools are quite complex. Finally, the EDA tools are industry standard and we wanted to complement this with an industry standard VHDL teaching package; this is the Esperan Multimedia HDL tutorials, which is normally delivered as an industry Master Class over 3 days.

We can see from Fig. 1 that the students are set up during the seminar before starting the self-based learning with MasterClass. There are 10 laboratory exercises in the MasterClass and the students are encouraged to cover at least the first 6, by which time they are reasonably familiar with simple VHDL concepts and the EDA tools. The teacher and laboratory demonstrators are on hand to provide support.

Seminar

During the seminar the students are introduced to the following material:

* course introduction;

* high level design with VHDL;

* introduction to VHDL;

* finite state machine design with VHDL;

* a practical VHDL-based design flow;

* design assignment.

Course introduction

During the seminar the students are introduced to all the teaching material they will use during the course. The students are issued with the course introduction sheets, which details in brief what they will encounter during the course, and the relevance of each topic is explained, see discussions below. The Esperan MasterClass Multimedia HDL tutorial package is issued to each student, signed for, and discussed. The students are allowed to use this at home. The Altera UPI FPGA board is shown and discussed.

High-level design with VHDL

A 1-hour presentation on high-level design with VHDL is given to introduce the students to the basic concepts they need to acquire during the laboratory session. This presentation covers typical ASIC- and FPGA-based top-down design flows using VHDL, comparison of schematics versus VHDL, other design methodologies and abstraction, basic VHDL concepts and application areas. We discuss each stage of the design flow: specification, partitioning, design entry, simulation, synthesis, and optimisation. It finishes with a closer look at VHDL - an illustration of a structural VHDL 3-bit adder subtractor is given - and the practical VHDL-based design flow the students will use.