Teaching digital controller design skills for embedded systems and mechatronics

International Journal of Electrical Engineering Education, Oct 2004 by Dell, Jonathan A

Abstract

This paper describes the ECAD work undertaken by third-year MEng students in the Department of Electronics at York in support of embedded systems and mechatronics. It describes in detail the digital electronics computer aided design (ECAD) element of the course where the students use Xilinx Foundation CAD to develop and test a simplified microprocessor.

Keywords digital controller design; embedded systems; hierarchical design; mechatronics; Xilinx(TM) ECAD

MEng courses in the Department of Electronics at the University of York are of four years' duration. In the final year students undertake a six-month research project either in industry or within one of the department's research groups. In preparation for this all the MEng students undertake a number of electronics CAD exercises as the principal academic component during the final term of their third-year studies. During this period the MEng students are also completing a software engineering group project where groups of about eight students work together on a large software development task; this develops group working skills that will be essential in their later careers.

The location of the ECAD exercises at this point in their programme of study is selected because it consolidates the third-year academic study and prepares them for their individual project work in the later part of the fourth-year studies. The core material in the electronics CAD exercises comprises numerical methods for ECAD, analogue ECAD using PSPICE and digital ECAD using Xilinx1 Foundation. Students additionally choose two from three optional ECAD exercises; these include control, communications and music, and are based around MATLAB and use appropriate SIMULINK toolboxes.

The main objective of the digital ECAD exercise is to gain first-hand experience of all stages in the digital design cycle and the principal task is to complete the design of a simplified microprocessor based around a 4-bit architecture. The work includes design entry by schematic capture and hardware description language (VHDL), functional and timing simulation. Also testing and fitting the design into a commercial field programmable gate array (FPGA) is required. Further objectives are:

* to gain an understanding of the hierarchical design approach which assists in the production of a complex system from the most primitive components;

* to obtain an insight into the details of processor operation; and

* to understand the development of effective test vectors in a hierarchical design.

On completion of the design the students can load the processor design into prototype hardware containing a Xilinx 4000 series FPGA. They can then observe the execution a few instructions in a simple program that activates the hardware in real time.

Digital ECAD laboratory work

A teaching laboratory containing about 30 PC workstations is utilised for all the ECAD practical sessions. Students work in pairs, as this is found to be the most effective learning environment. The digital ECAD laboratory work is undertaken during two-hour sessions each week over a seven-week period. This comparatively short period means that the laboratory work has to be carefully planned. Additionally, students are expected to spend at least two hours of their own time between sessions preparing for the work they will be doing in the following session. A rough breakdown of the activities undertaken in each of the sessions and a guideline of the essential intervening work is shown in Table 1. The students are provided with extensive notes covering the design task and reference material on the use of the hardware description language (VHDL) and the Xilinx development package. The student's work is carefully monitored during the first few sessions by inspecting their logbooks. If students do not make sufficient progress in the early stages of the module developments they can be issued with model worked solutions for the dualport register unit and the arithmetic unit thus enabling them to continue unimpeded with the rest of the work.

The simplified microprocessor design

The overall design is carefully chosen to include the main features of a typical microprocessor architecture without introducing unnecessary complexity. The chosen 4bit microprocessor design consists of four functional units, the controller, the data register, the arithmetic unit and the instruction memory. These units are interconnected by a top-level schematic that is provided to all the students as a starting point, this defines the architecture of the system and the detailed interconnection between the modules. The only unit for which the design has already been completed is the instruction memory and this is set up with a small program of instructions to furnish a rudimentary system test which allows the processor operation to be observed. A block diagram of the top-level design is shown in Fig. 1.

The register unit

The register unit consists of three 4-bit D-type register blocks, two of these form general purpose data registers and the third acts as the programme counter (PC) providing the instruction memory address. The students have to start by developing a generic master/slave latch design from basic gates as the latch in the Xilinx component library has inappropriate characteristics. A single level of hierarchy is used to combine four of these latches to form a 4-bit register block. Three of these blocks are further combined by another level of hierarchy to form the dual-port register unit. For simplicity the register control signals are not encoded so that all register outputs can be routed to either of the output buses A and B through appropriate arrangements of simple gates. Register input data is provided from a single input bus so further control inputs are required to determine which register is updated. The latch updating clock must be arranged so that data processed through the arithmetic unit can be written back to the same source register later in the same processor cycle. An asynchronous clear function is also required to initialise the system.