FPGA-based test bench for nonvolatile electronic memories

NASA Tech Briefs, Jul 2002

Multiple chips can be tested simultaneously at relatively low cost.

NASA's Jet Propulsion Laboratory, Pasadena, California

A test bench based on field-programmable gate arrays (FPGAs) has been developed to reduce the cost of testing nonvolatile memory circuits. Specifications for endurance testing of memories can require test times as long as weeks often impractically long in the case of commercial memory testers, which are expensive. The present FPGA-based test bench not only costs less than commercial memory testers do but can also be configured with multiple FPGAs to enable the simultaneous testing of many more memory chips than can be tested simultaneously on a commercial memory tester.

In comparison with the design of a commercial memory tester, the design of this test bench is more applicationspecific: The test bench is designed to perform certain reliability and endurance (life-cycle) tests on certain ferroelectric random-access memory (FRAM) and electrically erasable, programmable read-only memory (EEPROM) chips. The application-specific nature of the design offers advantages of lower cost, less complexity, and greater suitability for endurance testing. There is one disadvantage: Whereas a commercial memory tester can perform tests on many different types of memory chips without receding, the FPGA-based test bench must be recoded for different kinds of chips.

The test bench was developed by use of a commercial prototyping board and a commercial 10,000-gate FPGA. At present, the test bench can be configured to operate as either of two testers. The first tester performs a reliability test that detects address-decoder faults and stuck-at faults and that cycles through all of the addresses in a memory. The second tester performs an endurance test, in which it writes to, and reads back from, the same address repeatedly. The second tester can perform endurance tests faster than can a commercial memory tester, especially in cases of memory circuits that are slow by modern standards.

When an error is detected in a test, the data logged includes the error number, the address where the error occurred, the cycle number (where one cycle is defined as one read-and-write operation to a single address), the incorrect data value read, and (in the case of the reliability test) the portion of the test in which the error occurred. The error data can be logged by one of two methods. In the first method, which is applicable if the tester is connected to the parallel port of a personal computer, a small program written for this purpose sends the data to the computer screen and saves the data in a file. The second method, which is still undergoing development, would enable the tester to be totally independent of a personal computer. In this second method, the FPGA bit stream would be written into an EEPROM, which would be used to configure the FPGA on power-up. Instead of using a personal computer to log the error data, a light-emitting-diode display would be used to read out the error data when a switch was flipped. The display would also indicate whether testing was taking place, and whether an error had occurred.

This work was done by Jagdishbhai Patel, Jeffrey Namkung, and Vikram Rao of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Electronic Components and Systems category.

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