Design Automation Software Facilitates Radar Development
NASA Tech Briefs, Feb 2005
AccelChip® DSP Synthesis and AccelWare® IP
AccelChip Inc.
Milpitas, CA
408-943-0700
NASA's Jet Propulsion Laboratory in Pasadena, CA, purchased design automation tools from AccelChip to develop a digital filter for space-based radar applications. The DSP Synthesis and AccelWare IP provide a unified design environment in which high-performance DSP designs are achieved through an integrated flow. The products provide automated flows from MATLAB® algorithms to silicon. The toolset integrates with JPL's existing system-level verification tool for greater design efficiency.
The design automation tools will be used to shorten the design cycle and explore design alternatives, including performance and resource utilization, to obtain the level of optimization required in sensitive radar applications.
JPL will be using the MATLAB language to model the digital filter. The AccelChip algorithmic synthesis tool will then be used to automatically generate synthesizable, bit-accurate VHDL and Verilog from the MATLAB model, and provide a test bench for implementation and verification.
The software was chosen because it provided a design methodology similar to what JPL was already using to generate an onboard, range-compression, field-programmable gate array (FPGA). As a result, MATLAB can be used for both modeling and implementation, enabling JPL engineers to apply design changes easily and avoid costly redesign.
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