Interconnect Challenges for Nanoscale Electronic Circuits

JOM, Oct 2004 by Srivastava, Navin, Banerjee, Kaustav

This article provides an overview of the new challenges by nanometer-scale on-chip interconnects. Effects on performance and reliability are addressed, with an emphasis on resistivity, interconnect delay, and current-carrying capability.

INTRODUCTION

Transistors operate faster as their dimensions are scaled down. The wires on the chips that connect these transistors to form a circuit, however, do not exhibit the same benefit of scaling. The drive for faster chips with lower cost and greater functional ity has transformed these wires (interconnects) into what determines the performance and reliability of a nanometer-scale integrated circuit (IC). This paper provides an overview of the nanometer-scale interconnect issues beyond apparent technology scaling effects, with an emphasis on challenges beyond 90 nm.

NANOMETER-SCALE EFFECTS ON INTERCONNECTS

Resistivity

Copper has recently replaced aluminum as the dominant interconnect material. A drawback with copper, however, is the need for a diffusion barrier to prevent copper from diffusing into the surrounding dielectric. This film has much higher resistivity than copper, and -20% of the wire width can be consumed by the barrier film. In addition, wire cross-sectional dimensions are on the order of the mean free path of electrons (-40 nm at room temperature).1 At such dimensions, the electron-scattering effect at the conductor surface as well as at the grain boundaries cause its resistance to increase. Copper interconnect resistivity increases by several times over its bulk value (1.9 micro-ohm per centimeter at room temperature)1 at sub-90 nm technology nodes (Figure 1.)

Interconnect Delay

The intrinsic delay incurred on short-length wires has remained low compared to the logic gate delay. However, with the size effect mentioned previously, the local interconnect delay starts to increase significantly. Figure 2 compares the intrinsic local interconnect (traversing two contact plugs and two vias) delay with the logic delay. The local interconnect delay shows a sharp increase as the technology progresses beyond the 45 nm node, though it remains less prevailing than the gate delay. At the global level, however, the interconnect delay continues to dominate the logic delay as global signals traverse long distances across the chip. With technology scaling and added functionality, the number and length of these global lines increases. Since the delay of a long unbuffered line is quadratic in its length, long wires are divided into smaller segments using repeaters or buffers. The delay of an optimally buffered line is linear in its length.2 Hence, repeater insertion is an effective way to keep global wiring delay under control in IC design. Furthermore, the integration of low dielectric-constant materials can reduce interconnect capacitance and delay. Even with these techniques, however, the global signal delay constitutes one of the biggest challenges for future interconnects.3

For large high-performance designs, the number of repeaters can be prohibitively high4 (in excess of 106 for sub-90 nm designs). In general, the repeaters are optimally sized and separated. However, since these repeaters are large, the total power dissipation by such repeaters can be unacceptably large. The power dissipation is exacerbated by the substantial rise in leakage power beyond sub-90 nm technologies. It has been shown4 that by incurring a small delay penalty on global signal lines that do not lie on the critical timing path, a potential solution exists for large power savings by using smaller and fewer repeaters. The optimization scheme4 becomes important in nanometer-scale technologies where reduced power dissipation is a key performance criterion.

Current-Carrying Capability: Reliability

The current-carrying capacity of interconnects is limited by Joule heating andelectromigration (EM). Joule heating is affected by the resistance of the conducting wire. For contacts and local vias that have the smallest cross-sectional dimensions among on-chip interconnects, current-carrying capability is a concern. The current density required to be carried by local vias and contacts needs to increase at a much faster rate than that for other interconnects as technology scales beyond 90 nm.

The maximum allowable current density for interconnects is also dependent on EM lifetime, which is exponentially dependent on the metal temperature. Figure 3 shows thatEM and thermal constraints make the current density requirements unachievable beyond 45 nm technology node. (Arrows along the y-axis show current density needed to support International Technology Roadmap for Semiconductors (ITRS) requirements.) The metal temperature, in turn, is dependent on the junction (die) temperature of the chip. Due to threshold voltage scaling and process variations, leakage power dissipation has become a significant component of total chip power dissipation in nanometer scale-IC designs. Since the sub-threshold leakage current is exponentially dependent on temperature, the total chip power dissipation also becomes a function of temperature. This marks a significant departure from the traditional method of junction temperature evaluation. A complete methodology has been developed for the accurate computation of junction temperature using the electrothermal couplings between temperature, power, voltage, and frequency.5 These electrothermal couplings have direct implications on the metal temperature, and hence on the EM lifetime.